DFT 设计服务（DFT Design Service）

DFT（Design for Test）技术作为业界的标准手段，通过在芯片设计时加入测试专用电路，增加芯片的可测试性

简介

DFT（Design for Test）技术作为业界的标准手段，通过在芯片设计时加入测试专用电路，增加芯片的可测试性。如何降低测试成本，同时测试电路占用芯片设计上较小的面积，达到更高的故障覆盖率，已成为当前产业界的一个关键难题。
海洋之神590线路检测中心(中国区)官方网站-安全入口与子公司亿瑞芯联合推出可测性设计自动化和良率诊断解决方案及服务。成功案例包括国内多家头部的设计公司，产品涵盖MCU,ADAS, GPU, CPU,AI,5G, Video。用户可轻松应对复杂的SoC芯片、大规模芯片的诊断测试、汽车电子的功能性安全测试以及良率提升等挑战，取得质量与成本双赢。

Architecture Definition

Test Mode Definition
IO plan、Test Plan、Burn-In plan
MBIST、Repair、SCAN、Logic BIST、In-System-Test、BSCAN Structure Definition
3rd-party IP Test Interface Definition

Automotive DFT

In-System-Test
IST Controller and LBIST Controller Insertion
DMA Mode IST Integration to Support Power Self-test
CPU Interface IST Integration to Support Periodic Self-test
IST +MBIST+LBIST Verification
Low DPPM solution
Automotive Level ATPG
User Defined MBIST Algorithm
High Coverage Implementation( Scan Structure + Testpoint)

DFT Flow Development

DFT Insert：IST Controller、MBIST、Repair、BSCAN、IJTAG Network、OCC、Compress Structure、Logic BIST Controller Insertion
SCAN Insertion and Hierarchical ATPG
Pre-sim+Post-sim Simulation Environment
Formal Check、 DFT SDC Integration
Cell Aware ATPG、Diagnosis and Yield Improvement Flow

DFT Project Implementation

RTL Insertion
Block level and Top level Insertion for MBIST,Compress, OCC, BSCAN, LBIST, IST, IJTAG Network
Scan Insertion
SCAN Chain、Wrapper Cell Insertion and EDT Connection
ATPG
Graybox Generation and DC/AC ATPG
Simulation
MBIST、BSCAN、IJTAG Network、Chain/AC/DC Simulation
SDC
MBIST&AC Capture、Scan Shift、DC Capture SDC Generation，Flattern SDC Generation
Formal Check
Pre-DFT vs Post-DFT

Diagnosis and Yield Improvement

ATPG Diagnosis
Diagnosis Environment Setup
Chain Diagnosis Flow Build up
Layout Aware Scan Diagnosis
Transition Diagnosis
Cell Aware Diagnosis
Yield Analysis Flow Setup
MBIST Diagnosis
Build Lab MBIST Diagnosis
Build Mass Products MBIST Diagnosis